In interface circuits that transmit and receive data between circuit boards and between large scale integrated circuits, multiple-phase clocks are used for sampling data at a plurality of timings.
For example, in high-speed signal transmission systems, optimum timings for sampling data vary depending on losses of received signals and the strength of equalization processing. Ideal timings for sampling received signals are a timing of the center of data (the center of an eye) at which the received signal has the largest amplitude and a timing at which data makes a transition. However, after equalization processing, the largest amplitude is not obtained at the center of data in some cases. To address this, there is a way in which, using a function called an eye monitor, the phases of clocks for data sampling are changed (generating multi-phase clocks) and thus an optimum sampling timing is determined.
One approach for generating multi-phase clocks is a method of using a phase interpolator. A phase interpolator, using an accurate reference clock, enables phase adjustment to be performed accurately. However, a clock source for generating an accurate reference clock is used, and thus the cost and the circuit size increase.
Another approach for generating multi-phase clocks is a method of using a ring oscillator, or an injection locked ring oscillator in which an additional feature for improving jitter characteristics of a ring oscillator is added.
Examples of the related art are disclosed in Japanese Laid-open Patent Publication No. 2011-61325 and Japanese Laid-open Patent Publication No. 2013-106062.